Jimenez, Daniel individual record
Professor
Positions:
overview

I'm interested in anything related to making computation go faster. My focus is on microarchitecture and the interaction between the compiler and the microarchitecture. I've been doing a lot of work in branch prediction and more recently caches. I'm known for inventing the perceptron branch predictor as well as for other research.

selected publications
Academic Articles19
  • Jimenez, D. (2021). Top Picks From the 2020 Computer Architecture Conferences. IEEE Micro. 41(3), 6-9.
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  • AlBarakat, L. M., Gratz, P. V., & Jimenez, D. A. (2018). MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Computer Architecture Letters. 17(2), 175-178.
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  • Kim, J., Teran, E., Gratz, P. V., Jimnez, D. A., Pugsley, S. H., & Wilkerson, C. (2017). Kill the Program Counter. ACM SIGPLAN Notices. 52(4), 737-749.
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  • Jimnez, D., Labate, D., & Papadakis, M. (2016). Directional analysis of 3D tubular structures via isotropic well-localized atoms. Applied and Computational Harmonic Analysis. 40(3), 588-599.
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  • Liu, Q., Moreto, M., Abella, J., Cazorla, F. J., Jimenez, D. A., & Valero, M. (2016). Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Transactions on Architecture and Code Optimization. 12(4), 1-26.
Conference Papers58
  • Vavouliotis, G., Alvarez, L., Grot, B., Jiménez, D., & Casas, M. (2021). Morrigan: A Composite Instruction TLB Prefetcher. MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture. 1138-1153.
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  • Vavouliotis, G., Alvarez, L., Karakostas, V., Nikas, K., Koziris, N., Jimenez, D. A., & Casas, M. (2021). Exploiting Page Table Locality for Agile TLB Prefetching. 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 00, 85-98.
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  • Jamet, A. V., Alvarez, L., Jimenez, D. A., & Casas, M. (2020). Characterizing the impact of last-level cache replacement policies on big-data workloads. 2020 IEEE International Symposium on Workload Characterization (IISWC), 2020 IEEE International Symposium on Workload Characterization (IISWC). 00, 134-144.
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  • Grayson, B., Rupley, J., Zuraski, G. Z., Quinnell, E., Jimenez, D. A., Nakra, T., ... Ghiya, A. (2020). Evolution of the Samsung Exynos CPU Microarchitecture. 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). 40-51.
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  • Backes, L., & Jiménez, D. A. (2019). The impact of cache inclusion policies on cache management techniques. Proceedings of the International Symposium on Memory Systems, MEMSYS '19: The International Symposium on Memory Systems. 428-438.
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chaired theses and dissertations
Email
djimenez@tamu.edu
First Name
Daniel
Last Name
Jimenez
mailing address
Texas A&M University; Computer Science & Engineering; 3112 TAMU
College Station, TX 77843-3112
USA