overview
My research interests include computer-aided design of Very Large Scale Integration (VLSI) CAD, including physical design, parasitic extraction, fault diagnosis, variational analysis and process synthesis.
education and training
selected publications
Academic Articles28
- Zhou, Y., Zhang, Y., Sarin, V., Qiu, W., & Shi, W. (2016). Macro Model of Advanced Devices for Parasitic Extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35(10), 1721-1729.
- Li, Z., Zhou, Y. N., & Shi, W. (2012). O(mn) Time Algorithm for Optimal Buffer Insertion of Nets with m Sinks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(3), 437-441.
- Yi, Y., Wenzel, R., Sarin, V., & Shi, W. (2009). Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28(7), 1106-1110.
- Yi, Y., Wenzel, R., Sarin, V., & Shi, W. (2009). Inductance extraction for interconnects in the presence of nonlinear magnetic materials. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28(1), 1106-1110.
- Liu, Y., Hu, J., & Shi, W. (2008). Buffering Interconnect for Multicore Processor Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(12), 2183-2196.
Conference Papers52
- Huang, Y., Hu, J., & Shi, W. (2011). Lagrangian Relaxation for Gate Implementation Selection. Proceedings of the 2011 international symposium on Physical design. 167-174.
- Li, Z., Papa, D. A., Alpert, C. J., Hu, S., Shi, W., Sze, C., & Zhou, Y. (2010). Ultra-fast interconnect driven cell cloning for minimizing critical path delay. Proceedings of the 19th international symposium on Physical design. 75-82.
- Doddannagari, U., Hu, S., & Shi, W. (2009). Fast Characterization of Parameterized Cell Library. 2009 10th International Symposium on Quality of Electronic Design. 1, 500-505.
- Zhou, Y., Kanj, R., Agarwal, K., Li, Z., Joshi, R., Nassif, S., & Shi, W. (2009). The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield. Proceedings - International Symposium on Quality Electronic Design, ISQED, 2009 10th International Symposium on Quality Electronic Design. 607-+.
- Jiang, Z., & Shi, W. (2008). Circuit-wise buffer insertion and gate sizing algorithm with scalability. Design Automation Conference. 708-713.
recent teaching activities
- ECEN248 Intro To Dgtl Sym Dsgn Instructor
- ECEN454 Dig Integratedckt Des Instructor
- ECEN485 Directed Studies Instructor
- ECEN485 Directed Studies: In-ab Instructor
- ECEN491 Research Instructor
chaired theses and dissertations
- Chakraborty, Avijit (2015-11). Observability Driven Path Generation for Delay Test. (Master's Thesis)
- Gupta, Kaustubh (2013-07). Design, Simulation and Modeling of Insulated Gate Bipolar Transistor. (Master's Thesis)
- Bekal, Prasanna (2012-07). Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. (Master's Thesis)
- Huang, Yi-Le (2012-02). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization. (Master's Thesis)
Email
wshi@tamu.edu
First Name
Weiping
Last Name
Shi
mailing address
Texas A&M University; Electrical & Computer Engineering; 3128 TAMU
College Station, TX 77843-3128
USA