overview
Current research: optimization for energy-efficient VLSI circuits, on-chip communication fabrics, dynamic power management, adaptive circuit design, interactions between physical design and system-level design, heuristics for large scale combinatorial optimization.
education and training
- Ph.D. in Electrical Engineering, University of Minnesota - (Minneapolis, Minnesota, United States) 2001
- M.S. in Physics, Zhejiang University - (Hangzhou, Zhejiang, China) 1997
- B.S. in Optical Engineering, Zhejiang University - (Hangzhou, Zhejiang, China) 1990
selected publications
Academic Articles64
- Zhuo, C., Luo, S., Gan, H., Hu, J., & Shi, Z. (2020). Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(7), 1498-1510.
- Sengupta, D., Snigdha, F. S., Hu, J., & Sapatnekar, S. S. (2019). An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38(1), 70-83.
- Lee, S., Shi, C., Wang, J., Sanabria, A., Osman, H., Hu, J., & Sanchez-Sinencio, E. (2018). A Built-In Self-Test and
In Situ Analog Circuit Optimization Platform. IEEE Transactions on Circuits and Systems I: Regular Papers. 65(10), 3445-3458. - Wang, Y., Chen, P. u., Hu, J., Li, G., & Rajendran, J. (2018). The Cat and Mouse in Split Manufacturing. IEEE Transactions on Very Large Scale Integration Systems. 26(5), 805-817.
- Won, J., Gratz, P. V., Shakkottai, S., & Hu, J. (2016). Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Transactions on Design Automation of Electronic Systems. 21(4), 1-25.
Chapters5
- Liu, Y., & Hu, J. (2011). GPU-Based Parallel Computing for Fast Circuit Optimization. GPU Computing Gems Emerald Edition. 365-378. Elsevier.
- Hu, J., Li, Z., & Hu, S. (2008). Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation. Taylor & Francis.
- Hu, J., & Sze, C. (2008). Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation. Taylor & Francis.
- Hu, J., Robins, G., & Sze, C. (2008). Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation. Taylor & Francis.
- Hu, J., & Sapatnekar, S. S. (2001). Non-Hanan Optimization for Global VLSI Interconnect. Lu, B., Du, D., & Sapatnekar, S. S. (Eds.), Layout Optimization in VLSI Design. 89-123. Springer Nature.
Conference Papers109
- Li, C., Sapatnekar, S. S., & Hu, J. (2019). Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED, 20th International Symposium on Quality Electronic Design (ISQED). 00, 33-38.
- Xie, Z., Huang, Y., Fang, G., Ren, H., Fang, S., Chen, Y., & Hu, J. (2018). RouteNet: Routability Prediction for Mixed -Size Designs Using Convolutional Neural Network. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design, Proceedings of the International Conference on Computer-Aided Design. 1-8.
- Feng, L., Kudva, P., Da Silva, D., & Hu, J. (2018). Exploring Serverless Computing for Neural Network Training. IEEE International Conference on Cloud Computing, CLOUD, 2018 IEEE 11th International Conference on Cloud Computing (CLOUD). 2018-July, 334-341.
- Huang, L., Hou, I., Sapatnekar, S. S., & Hu, J. (2018). Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. Proceedings of the 26th International Conference on Real-Time Networks and Systems. 159-169.
- Jayasankaran, N. G., Borbon, A. S., Sanchez-Sinencio, E., Hu, J., & Rajendran, J. (2018). Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design, Proceedings of the International Conference on Computer-Aided Design. 1-8.
researcher on
Principal Investigator4
- RTML: Small: Real-Time Model-Based Bayesian Reinforcement Learning awarded by National Science Foundation 2019 - 2022
Co-Principal Investigator2
awards and honors
recent teaching activities
- CSCE491 Hnr-research Instructor
- CSCE491 Research Instructor
- CSCE684 Professional Internship Instructor
- CSCE684 Professional Internship: In-ab Instructor
- CSCE684 Professional Internship:in-ab Instructor
chaired theses and dissertations
- Bhosekar, Shilpa (2018-08). Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip. (Master's Thesis)
- Puli, Ramprakash Reddy (2018-05). Active Routing: Compute on the Way for Near-Data Processing. (Master's Thesis)
- Li, Chaofan (2018-05). Synthesis Techniques for Power-Efficient Integrated Circuits. (Doctoral Dissertation)
- Wang, Jiafan (2017-08). Adaptive Integrated Circuit Design for Variation Resilience and Security. (Doctoral Dissertation)
- Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform. (Master's Thesis)
Email
jianghu@tamu.edu
First Name
Jiang
Last Name
Hu
mailing address
Texas A&M University; Electrical Engineering; 3128 TAMU
College Station, TX 77843-3128
USA