Hu, Jiang individual record
Professor
overview

Current research: optimization for energy-efficient VLSI circuits, on-chip communication fabrics, dynamic power management, adaptive circuit design, interactions between physical design and system-level design, heuristics for large scale combinatorial optimization.

education and training
selected publications
Academic Articles63
  • Sengupta, D., Snigdha, F. S., Hu, J., & Sapatnekar, S. S. (2019). An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 38(1), 70-83.
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  • Lee, S., Shi, C., Wang, J., Sanabria, A., Osman, H., Hu, J., & Sanchez-Sinencio, E. (2018). A Built-In Self-Test and In Situ Analog Circuit Optimization Platform. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 65(10), 3445-3458.
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  • Wang, Y., Chen, P. u., Hu, J., Li, G., & Rajendran, J. (2018). The Cat and Mouse in Split Manufacturing. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 26(5), 805-817.
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  • Won, J., Gratz, P. V., Shakkottai, S., & Hu, J. (2016). Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Transactions on Design Automation of Electronic Systems. 21(4), 1-25.
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  • Silva-Martinez, J., Karsilayan, A. I., Hu, J., & Krishnaswamy, H. (2016). Special Issue on the 57th International Midwest Symposium on Circuits and Systems. Analog Integrated Circuits and Signal Processing. 88(2), 181-183.
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Chapters5
  • Liu, Y., & Hu, J. (2011). GPU-based parallel computing for fast circuit optimization. GPU Computing Gems Emerald Edition. (pp. 365-378). Elsevier.
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  • Hu, J., Li, Z., & Hu, S. (2008). Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation. Auerbach Publications.
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  • Hu, J., & Sze, C. (2008). Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation. Auerbach Publications.
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  • Hu, J., Robins, G., & Sze, C. (2008). Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation. Auerbach Publications.
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  • Hu, J., & Sapatnekar, S. S. (2001). Non-Hanan Optimization for Global VLSI Interconnect. Lu, B., Du, D., & Sapatnekar, S. S. (Eds.), Network Theory and Applications. (pp. 89-123). Springer Us.
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Conference Papers109
  • Li, C., Sapatnekar, S. S., Hu, J., & IEEE, .. (2019). Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. 2019-March, 33-38.
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  • Feng, L., Kudva, P., Da Silva, D., Hu, J., & IEEE, .. (2018). Exploring Serverless Computing for Neural Network Training. IEEE International Conference on Cloud Computing, CLOUD. 2018-July, 334-341.
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  • Huang, L., Hou, I. H., Sapatnekar, S. S., & Hu, J. (2018). Graceful degradation of low-criticality tasks in multiprocessor dual-criticality systems. 159-169.
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  • Xie, Z., Huang, Y., Fang, G., Ren, H., Fang, S., Chen, Y., Hu, J., & Machinery, A. C. (2018). RouteNet: Routability Prediction for Mixed -Size Designs Using Convolutional Neural Network. 2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD).
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  • Jayasankaran, N. G., Borbon, A. S., Sanchez-Sinencio, E., Hu, J., Rajendran, J., & Machinery, A. C. (2018). Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. 2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD). 7-7.
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chaired theses and dissertations
Email
jianghu@tamu.edu
First Name
Jiang
Last Name
Hu
mailing address
Texas A&M University; Electrical Engineering; 3128 TAMU
College Station, TX 77843-3128
USA