Walker, Duncan
individual record
Professor - Term Appointment
Positions:
- Professor and Graduate Advisor, Computer Science and Engineering, College of Engineering
education and training
- Ph.D. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1986
- M.S. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1984
- B.S. in Engineering (Honors), California Institute of Technology - (Pasadena, California, United States) 1979
selected publications
Academic Articles23
- Zhang, T., Gao, Y., & Walker, D. (2015). Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing: Theory and Applications (JETTA). 31(1), 99-106.
- Gao, Y., Zhang, T., Pokharel, P., Chakraborty, S., & Walker, D. (2014). Pseudo Functional Path Delay Test through Embedded Memories. Journal of Electronic Testing: Theory and Applications (JETTA). 31(1), 35-42.
- Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D. (2008). A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration. 41(3), 399-412.
- Wang, J., Walker, D. M., Lu, X., Majhi, A., Kruseman, B., Gronthoud, G., ... Eichenberger, S. (2007). Modeling Power Supply Noise in Delay Testing. IEEE Design and Test. 24(3), 226-234.
- Sabade, S. S., & Walker, D. (2006). Estimation of Fault-Free Leakage Current Using Wafer-Level Spatial Information. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14(1), 91-94.
Chapters4
- Walker, D. M., & Hsiao, M. S. (2008). Chapter 6 Delay Testing. System-on-Chip Test Architectures. (pp. 263-306).
- Huang, J. L., Li, J., & Walker, D. M. (2006). Logic and fault simulation. VLSI Test Principles and Architectures. (pp. 105-159). Elsevier.
- Huang, J., Li, J., & Walker, D. M. (2006). Chapter 3 Logic and Fault Simulation. VLSI Test Principles and Architectures. (pp. 105-159).
- Sakallah, K. A., Walker, D. M., & Nassif, S. R. (2003). Timing, Test and Manufacturing Overview. The Best of ICCAD. (pp. 551-562). Springer US.
Conference Papers78
- Chakraborty, A., & Walker, D. (2020). Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. 00, 1-4.
- Biswas, P., & Walker, D. (2017). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 141-146.
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- Chakraborty, A., & Walker, D. (2015). Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. 20-22-May-2015, 397-402.
researcher on
Principal Investigator1
Investigator1
awards and honors
recent teaching activities
- CSCE491 Hnr-research Instructor
- CSCE491 Research Instructor
- CSCE606 Software Engineering Instructor
- CSCE680 Test & Diag Digital Syst Instructor
- CSCE684 Professional Internship: In-ab Instructor
chaired theses and dissertations
- Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform. (Master's Thesis)
- Biswas, Prasenjit (2016-08). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. (Master's Thesis)
- Boga, Viswanath (2016-05). Optimization of Pseudo Functional Path Delay Test Through Embedded Memories. (Master's Thesis)
- Chakraborty, Avijit (2015-12). Observability Driven Path Generation for Delay Test. (Master's Thesis)
- Zhang, Tengteng (2015-12). High Quality Test Generation Targeting Power Supply Noise. (Doctoral Dissertation)
Email
d-walker@tamu.edu
First Name
Duncan
Last Name
Walker
mailing address
Texas A&M University; Computer Science & Engineering; 3112 TAMU
College Station, TX 77843-3112
USA