Walker, Duncan individual record
Professor - Term Appointment
Positions:
selected publications
Academic Articles23
  • Zhang, T., Gao, Y., & Walker, D. (2015). Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing. 31(1), 99-106.
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  • Gao, Y., Zhang, T., Pokharel, P., Chakraborty, S., & Walker, D. (2015). Pseudo Functional Path Delay Test through Embedded Memories. Journal of Electronic Testing. 31(1), 35-42.
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  • Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D. (2008). A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration. 41(3), 399-412.
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  • Jing Wang, .., Walker, D. M., Xiang Lu, .., Majhi, A., Kruseman, B., Gronthoud, G., ... Eichenberger, S. (2007). Modeling Power Supply Noise in Delay Testing. IEEE Design & Test of Computers. 24(3), 226-234.
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  • Sabade, S. S., & Walker, D. (2006). Estimation of fault-free leakage current using wafer-level spatial information. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14(1), 91-94.
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Chapters4
  • Walker, D. M., & Hsiao, M. S. (2008). Chapter 6 Delay Testing. System-on-Chip Test Architectures. 263-306.
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  • Huang, J., Li, J., & (Hank) Walker, D. M. (2006). Logic and Fault Simulation. VLSI Test Principles and Architectures. 105-159. Elsevier.
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  • Huang, J., Li, J., & Walker, D. M. (2006). Chapter 3 Logic and Fault Simulation. VLSI Test Principles and Architectures. 105-159.
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  • Sakallah, K. A., Walker, D. M., & Nassif, S. R. (2003). Timing, Test and Manufacturing Overview. The Best of ICCAD. 551-562. Springer US.
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Conference Papers78
  • Chakraborty, A., & Walker, D. (2020). Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 00, 1-4.
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  • Biswas, P., & Walker, D. (2017). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID). 141-146.
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  • Zhang, T., & Walker, D. (2015). Impact of test compression on power supply noise control. 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). 161-166.
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  • Chakraborty, S., & Walker, D. (2015). At-Speed Path Delay Test. 2015 IEEE 24th North Atlantic Test Workshop, 2015 IEEE 24th North Atlantic Test Workshop (NATW). 39-42.
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  • Chakraborty, A., & Walker, D. (2015). Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLSVLSI '15: Great Lakes Symposium on VLSI 2015. 20-22-May-2015, 397-402.
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chaired theses and dissertations
Email
d-walker@tamu.edu
First Name
Duncan
Last Name
Walker
mailing address
Texas A&M University; Computer Science & Engineering; 3112 TAMU
College Station, TX 77843-3112
USA