Palermo, Samuel individual record

My research focuses on developing novel, energy-efficient, high-performance mixed-signal integrated circuit architectures in nanometer CMOS technologies. Specifically, my research interests cover the following areas:

1) High-speed electrical and optical chip-to-chip and on-chip interconnect architectures,

2) Clocking and synchronization circuits and systems,

3) Robust analog circuit design with digital-assistance techniques to address increasing process variability in highly-scaled CMOS technologies,

4) Sensor circuits for emerging applications.

education and training
selected publications
Academic Articles46
  • Kiran, S., Cai, S., Zhu, Y., Hoyos, S., & Palermo, S. (2019). Digital Equalization With ADC-Based Receivers. IEEE Microwave Magazine. 20(5), 62-79.
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  • Roshan-Zamir, A., Iwai, T., Fan, Y., Kumar, A., Yang, H., Sledjeski, L., ... Palermo, S. (2019). A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS. IEEE Journal of Solid-State Circuits. 54(3), 672-684.
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  • Palermo, S., & Sun, N. (2019). Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference. IEEE Journal of Solid-State Circuits. 54(3), 611-612.
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  • Kiran, S., Shafik, A., Tabasy, E. Z., Cai, S., Lee, K., Hoyos, S., & Palermo, S. (2019). Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization. IEEE Transactions on Components Packaging and Manufacturing Technology. 9(3), 536-548.
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  • Kiran, S., Cai, S., Luo, Y., Hoyos, S., & Palermo, S. (2018). A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. IEEE Journal of Solid-State Circuits. 54(3), 659-671.
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  • Li, C., Gratz, P. V., & Palermo, S. (2015). Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors. More than Moore Technologies for Next Generation Computer Design. 155-186. Springer New York.
  • Palermo, S. M. (2011). High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems. Iniewski, K. (Eds.), CMOS Nanoelectronics: Analog and RF VLSI Circuits. McGraw-Hill.
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Conference Papers89
  • Kiran, S., Cai, S., Luo, Y., Hoyos, S., & Palermo, S. (2019). A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC). 00, 1-4.
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  • Fan, Y., Kumar, A., Iwai, T., Roshan-Zamir, A., Cai, S., Sun, B. o., & Palermo, S. (2019). A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS. 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC). 00, 1-4.
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  • Fan, Y. H., Liang, D., Roshan-Zamir, A., Zhang, C., Wang, B., Fiorentino, M., Beausoleil, R., & Palermo, S. (2019). A Directly Modulated Quantum Dot Microring Laser Transmitter with Integrated CMOS Driver.
  • Li, C., Yu, K., Rhim, J., Zhu, K., Qi, N., Fiorentino, M., ... Palermo, S. (2018). A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. 00, 32-35.
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  • Kiran, S., Cai, S., Hoyos, S., & Palermo, S. (2018). Statistical Modeling of Non-Linearity in Decision Feedback Equalizer-Based Mixed-Signal Receivers. 2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS). 00, 29-31.
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chaired theses and dissertations
First Name
Last Name
mailing address
Texas A&M University; Electrical Engineering; 3128 TAMU
College Station, TX 77843-3128