Scholars

Assistant Professor

Positions:

UN Sustainable Development Goals:

Map of Science

UN Sustainable Development Goals:

education and training

selected publications

Jayasankaran, N. G., Borbon, A. S., Sanchez-Sinencio, E., Hu, J., & Rajendran, J. (2022). Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING. 10(1), 386-403.
Devadas, S., & Rajendran, J. (2022). Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security. IEEE DESIGN & TEST. 39(4), 5-6.
Sanabria-Borbon, A., Jayasankaran, N. G., Hu, J., Rajendran, J., & Sanchez-Sinencio, E. (2021). Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS. 68(1), 36-41.
Garg, S., Holcomb, D., Rajendran, J., & Sadeghi, A. (2021). Guest Editors' Introduction: Competing to Secure SoCs. IEEE DESIGN & TEST. 38(1), 5-6.

SDG 3
Gohil, V., Tressler, M., Sipple, K., Patnaik, S., & Rajendran, J. (2021). Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing. IEEE Transactions on Information Forensics and Security. 16, 5077-5092.

Jayasankaran, N. G., Sanabria-Borbn, A., Snchez-Sinencio, E., Hu, J., & Rajendran, J. (2020). Analog IP Protection and Evaluation. Emerging Topics in Hardware Security. 419-469. Springer Nature.
Yasin, M., Rajendran, J., & Sinanoglu, O. (2020). Discussion.. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES. 131-132. Wolters Kluwer.
Yasin, M., Rajendran, J., & Sinanoglu, O. (2020). A Brief History of Logic Locking. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES. 17-31. Springer International Publishing.
Yasin, M., Rajendran, J., & Sinanoglu, O. (2020). Appendix A Background on VLSI Test. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES. 139-142.
Yasin, M., Rajendran, J., & Sinanoglu, O. (2020). Approximate Attacks. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES. 69-76. Springer International Publishing.

Gohil, V., Guo, H., Patnaik, S., & Rajendran, J. (2022). ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security. 1275-1289.
Bhunia, S., Das, A., Fazzari, S., Kammler, V., Kehlet, D., Rajendran, J., & Srivastava, A. (2022). Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design. 1-8.
Rajendran, J. (2022). Session details: The Role of Graph Neural Networks in Electronic Design Automation. Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design.
Patnaik, S., Gohil, V., Guo, H., & Rajendran, J. J. (2022). Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. 2022 19th International SoC Design Conference (ISOCC), 2022 19th International SoC Design Conference (ISOCC). 00, 217-218.
Gohil, V., Patnaik, S., Guo, H., Kalathil, D., & Rajendran, J. J. (2022). DETERRENT. Proceedings of the 59th ACM/IEEE Design Automation Conference, Proceedings of the 59th ACM/IEEE Design Automation Conference. 697-702.