2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS | Conference Paper individual record
abstract

Supply-voltage scaling has become one of the most effective methods to improve the energy efficiency of power-constrained systems, motivating its application towards high-performance I/O links [1]. Due to the accelerating need for more off-chip I/O bandwidth, it is desirable to provide both higher data rate and low-VDD operation to achieve optimal energy efficiency. Unfortunately, efficient implementations of equalization circuits are one of the major challenges faced in >10Gb/s serial-link systems that attempt to incorporate reduced-supply operation. For example, a continuous-time linear equalizer (CTLE), due to its analog nature, exhibits a rapid degradation in gain/bandwidth and only linear power scaling when operating at low V DD. Decision-feedback equalizers (DFEs) also have to make significant compromise of speed from longer delay in the critical feedback path. Consequently, previous >10Gb/s equalizers have not pursued extensive supply voltage scaling [2-5]. © 2014 IEEE.

author list (cited authors)
Bai, R., Palermo, S., & Chiang, P. Y.
publication date
2014
publisher
IEEE Publisher
citation count

9